(a) Field of the Invention
The present invention relates to an area-array semiconductor device having arranged external electrode terminals on the bottom surface of a chip or the bottom surface of a package, and more in detail to the semiconductor device having a reduced size of the chip or the package and to increase the number of the external electrode terminals.
(b) Description of the Related Art
With the higher integration of a semiconductor device, the number of external electrode terminals for externally and electrically connecting a chip or a package mounting the chip is increased. On the other hand, the miniaturization of the chip or the package is advanced to reduce the size of the pitch between the terminals of internal electrode terminals. Accordingly, the pitch of the interconnect pads formed on a packaging substrate or a mounting board for packaging the chip thereon is also reduced, and the reduced pitch makes it difficult to arrange the interconnects on the packaging substrate or mounting board. As a result, the miniaturization of the chip and the package is hardly realized.
A semiconductor device 101 as shown in FIG. 1 is an example of forming internal electrode terminals on the bottom surface of a chip 103 which is mounted on a packaging substrate 102. A plenty of ball electrodes 131 acting as external electrode terminals are arranged on the bottom surface of the chip 103 in a BGA (ball grid array) arrangement. The packaging substrate 102 includes, on the top surface thereof, interconnect pads 121 corresponding to the ball electrodes 131 of the chip 103 and interconnect lines 122 for connecting the respective interconnect pads 121. On the bottom surface of the packaging substrate 102 are arranged packaging ball electrodes 124 connected to the interconnect pads 121 and the interconnect lines 122 through intermediary of via-plugs 123. The chip 103 is mounted over the packaging substrate 102 and covered and sealed with resin 105, and the ball electrodes 131 of the chip 103 are connected to the interconnect pads 121 by soldering. The semiconductor device 101 is mounted on a substrate 104, and the packaging ball electrodes 124 are connected to interconnects pads 141 formed on the top surface of the substrate 104.
The interconnect pads 121 arranged on the packaging substrate 102 surface as shown in FIG. 2 are substantially identical with the ball electrodes 131 formed on the bottom surface of the chip 103 with respect to their arrangements. The conventional interconnect pad arrangement has so-called peripherals including a signal line terminal (S-terminal), a power source terminal (V-terminal) and a ground terminal (G-terminal) arranged on a single line and disposed in a region corresponding to the outer peripheral of the chip 103. As shown in FIG. 2, the respective interconnect pads 121 including the S-terminal, the V-terminal and the G-terminal are arranged in the shape of a lattice by keeping specified intervals. Each of interconnect lines 122 is connected to each of the interconnect pads 121, and extends toward the outer region of the chip. The interconnect lines 122 connected to the interconnect pads 121 existing in the inner part outwardly extend between the interconnect pads 121 existing in the outer part, and the front end of the interconnect line 122 is electrically connected to the packaging ball electrodes 124 on the bottom surface of the packaging substrate 102 through intermediary of the via-plugs 123 as shown in FIG. 1.
However, in the arrangement of the above interconnect pads, due to the density of the interconnect pads 121 and the interconnect lines 122 as shown in FIG. 3, the number of the interconnect lines 122 extending from the inner interconnect pads 121 is restricted because the diameter of the interconnect pad 121 is generally larger than the width of the interconnect lines 122 and the interval of the adjacent lines.
When the interconnect pads 121 having a diameter of 100 μm are arranged at a pitch of 250 μm, only two interconnect lines 122 can be drawn when the line width of the interconnect lines 122 is 30 μm and the line interval is 30 μm. In other words, only 12 interconnect lines 122 can be arranged in an area having a width of 1 mm in the above structure of the interconnect pads 121, and the density of the interconnect lines is 12 lines/mm. When the number of the interconnect pads is increased to increase the number of the interconnect lines, the pitch of the interconnect pads is required to be larger than 250 μm as described above or the chip size is required to be larger, thereby hardly realizing the miniaturization of the chip and the packaging substrate because the larger area is necessary to arrange the interconnect pads.
In order to solve such a problem, JP-A-10(1998)-116859 describes a technique in which interconnects pads for a standard power and a standard current which do not receive nor supply signals are disposed inside a package (chip) and the interconnects pads are connected to external connecting terminals just below the chip. In the configuration, since the interconnect pad which does not receive nor supply signals is not required to be connected to the interconnect line, the interconnect line to be arranged among the interconnect pads is unnecessary, thereby reducing the interval between the adjacent interconnect pads. As a result, the number of the interconnect pads can be increased and the miniaturization of the chip can be attained.
JP-A-9(1997)-69568 describes a technique in which an input-output buffer is disposed in an open region occurring in an inner circuit block-disposing area by not distinguishing an input-output buffer disposing area from the inner circuit block-disposing area in order to realize the configuration which effectively utilizes the open area occurring in the inner circuit blocks without deteriorating the fundamental algorism of a tool for automatically disposing interconnects when the input-output buffer and the inner circuit block are disposed on the chip. When the technique is applied on the chip or the package, at least the freedom of the disposition with respect to the disposition of the interconnect pads is elevated to effectively implement the miniaturization.
However, in the former publication, the number of the interconnect pads which do not receive nor supply signals is assumed not to be small. Accordingly, the technique cannot be applied when the number of the interconnect pads of this kind is small and most part of interconnect pads are required to be connected to interconnect lines. If the technique is applied to part of the interconnect pads, the number of the interconnect lines externally drawn is restricted.
In the latter publication, the number of the input-output buffers depends on the open area occurring among the inner circuit blocks, and when the open areas are concentrated, it is uncertain that the interconnect lines are drawn from the input-output buffers. Accordingly, the interconnect pads must be designed for every floor plan to increase a period of time. When the drawing-out of the interconnect lines is hardly attained, the effective means for responding thereto does not exist.
In the above technique, the interconnect line formed on the packaging substrate is assumed to be a single layer. When the interconnect line formed on the packaging substrate is made to be a multi-layered structure having two or more layers, the structure increases the freedom of arranging the interconnect lines to assist to solve the above problem. However, the multi-layered structure may make the interconnect lines of the upper layer and the lower layer crossed with each other to hardly perform the impedance matching among the interconnect lines, thereby affecting larger adverse effects on the semiconductor device.